1. Field of the Invention
The invention relates to a data processing pipeline system and method utilizing a cascade of data processing modules for processing successive groups of data units (units of data), relevant to the processing, which are presented to a system input, said groups being separated from one another by time slots, and a control signal generator for supplying the modules with at least one control signal for controlling the processing by the modules, which control signal occurs in synchronism with the presence of each group at the system input.
2. Description of the Related Art
A pipeline system of this kind is known from European Patent Application EP-A 0285192 which corresponds to commonly owned U.S. Pat. No. 4,916,659. The known pipeline system is an image processing system in which an image is generated by means of the frame scan method. Therein, an image is composed of successive lines, each of which comprises successive pixels. The time slots comprise dead time intervals which are produced, for example by the line fly-back and frame fly-back occurring during image acquisition (see, for example the FIGS. 2 and 3 of EP-A-0285192). In the known system the control signals are applied to the modules in parallel and are delayed in each module by a relevant delay generator in accordance with the cumulative delay incurred by the already processed data due to the processing in the preceding modules. The delay of the control signals maintains synchronization between the data and the control signals.
Even though the known system can be readily reconfigured and has a simple set-up, the solution chosen to solve the synchronization problem implies that each module must be provided with a delay operator for the control signals in order to prevent, for example, the occurrence of time slots from disturbing the data processing.
Another solution for the mutual synchronization of data and control signals could consist in delaying the data per module so that they remain synchronized with the control signals. Like in the previous solution, additional operators are then required for delaying the data. An additional drawback consists in that the overall pipeline processing time is thus increased.
Another solution, for example in the case where the control signals are sampling signals, would be the resampling of the data. This has the drawback that resampling requires additional arithmetic units for interpolation, thus introducing additional processing delays in the system.